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【分享】Tensilica公司的介绍

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发表于 2016-12-21 13:44 | 显示全部楼层 |阅读模式
Tensilica 是一个迅速成长的公司,公司主要产品是在专业性应用程序微处理器上, 为现今高容量嵌入式系统提供最优良的解决方案。 公司成立于1997年7月。
公司简介

公司创始的几名主要干部与高级经理都学有专精。 其专业技术包括有四个领域: 微处理器构架、 ASIC 与VLSI 设计、 高级软件开发与电子设计自动化(EDA)。 本公司率先研发出世界第一个可以自由装组、 可以弹性扩张的微处理器构架;并提供一个技术支持环境, 让嵌入式系统工程师可以用最少的时间做出性能更好、 集成度更高的单芯片系统。
1998 年后半年, Tensilica 开始与初期顾客密切合作, 到1999 年2 月公开推出标竿产品── 一系列可以自由装组、 可以弹性扩张的处理器产品。
该公司的投资者包括三家声名卓著的创投公司: Oak Investment Partners, Worldview Technology Partners 和 Foundation Capital, 与高科技电子业内著名的五家公司: Cisco Systems, Inc., Matsushita Electric Industrial Company Ltd., Altera Corporation, NEC Corporation 和 Conexant Systems。
产品介绍

Tensilica 公司的 Xtensa 处理器是一个可以自由装组、可以弹性扩张,并可以自动合成的处理器核心。Xtensa 是第一个专为嵌入式单芯片系统而设计的微处理器。为了让系统设计工程师能够弹性规划、 执行单芯片系统 的各种应用功能,Xtensa 在研发初期就已锁定成一个可以自由装组的架构。
Xtensa 处理器具有不同于其它传统式的嵌入式处理器核心,改变了单芯片系统的设计规则。采用 Xtensa 的技术时,系统设计工程师可以挑选所需的单元架构,再加上自创的新指令与硬件执行单元,就可以设计出比其它传统方式强大数倍的处理器核心。Xtensa 生产器可以针对每一个处理器的特殊组合,自动有效地产生出一套包括操作系统,完善周全的软件工具。可以自由装组的 Xtensa 处理器,其设计方式弹性大,功效高,是所有高合成的单芯片系统的最佳选择。
Xtensa的指令集构架 (ISA) 拥有专利权。这个现代化的32位处理器的结构特色是有一套专门为嵌入式系统设计、精简而高效能的16与24位指令集。其基本结构拥有80个 RISC 指令,其中包括32位 ALU,6个管理特殊功能的寄存器,32或64个普通功能32位寄存器。这些32位寄存器都设有加速运作功能的窗口。Xtensa 处理器的结构技术先进、指令精简,可以帮助系统设计师大量缩减编码的长度,从而提高指令的密集度并降低能耗。这对于高合成的单芯片系统 ASIC 而言,是减低成本的重要关健。Xtensa 的指令集构架包括强劲的分支指令,例如:经合成的比较 - 分歧循环、零开销循环和二进制处理,包括漏斗切换和字段抽段操作等。浮动点单元与矢量 DSP 单元是 Xtensa 结构上两个可以加选的单元。
要更进一步了解 Xtensa 处理器的功能,请访问该公司的英文网站。 http://ip.cadence.com


Cadence公司宣布3.8亿美元现金收购IP供应商Tensilica,这不仅是Cadence公司有史以来最大一次收购,同时也是其历史上最高估值的一次收购。Tensilica公司2012年销售额为4400万美元,收购价超过其营业额的八倍。通过此次收购,Cadence公司的IP业务可超过1亿美元。此前的2010年,Cadence收购了IP验证公司Denali,而在上个月,其又收购了IP供应商Cosmic Circuits。
Tensilica在过去十六年间曾经有六次融资,融资规模达到1亿美元,投资方包括FoundationCapital、Altera、思科以及其他。公司客户包括英特尔、博通、思科、三星等等。Qatalyst Partners是此次收购的第三方顾问。
Tensilica的核心IP为可配置处理器,被广泛应用于手机及网络通信设施中。

Tensilica
Tensilica Inc.

Subsidiary
Industry
Founded
1997
Headquarters
San Jose, California
Key people
Chris Rowen, Jack Guedj
Products
Microprocessors, Hifi audio, DSP cores
Websiteip.cadence.com
[color=rgba(0, 0, 0, 0.701961)]Tensilica is a company based in Silicon Valley in the semiconductor intellectual property core business. It is now a part of Cadence Design Systems. Its dataplane processors (DPUs) combine the strengths of CPUsand DSPs and custom logic with 10 to 100 times the performance[citation needed], making them suited for data-intensive processing tasks.
[color=rgba(0, 0, 0, 0.701961)]Tensilica is known for its customizable microprocessor core, the Xtensa configurable processor. Other products include: HiFi audio/voice DSPs with a software library of over 125 codecs from Cadence and over 55 software partners; IVP Image/Video DSP, designed to handle complex algorithms in imaging, video and computer vision; and ConnX family of baseband DSPs ranging from the dual-MAC ConnX D2 to the 64-MAC ConnX BBE64EP.
[color=rgba(0, 0, 0, 0.701961)]Tensilica was founded in 1997 by Chris Rowen (one of the founders of MIPS Technologies) and was initially staffed by former employees of several other Silicon Valley processor and electronic design automation companies. It employed Earl Killian, who contributed to the MIPS instruction set, as chief software architect for several years.[1] On March 11, 2013, Cadence Design Systems announced its intent to buy Tensilica for approximately $380 million in cash.[2] Cadence completed the acquisition in April 2013, with a cash outlay at closing of approximately $326 million. [3]

Cadence Tensilica products
Cadence Tensilica develops SIP blocks to be included on the dies of products of their licensees, such as system on a chipsfor embedded systems, particularly in mobile, home entertainment, and communications.
Xtensa configurable cores
An Xtensa DPU (data plane processing unit) can be employed as anything from a small, low-power cache-less microcontroller to a high-performance 16-way SIMD, 3-issue VLIW DSP core.
IP processor vendors such as Tensilica typically offer their licensees the choice between many of the IP core's implementation details: cache size, processor bus width, data and instruction RAMs, memory management and interrupt control. However, Cadence's Xtensa architecture offers a key differentiating feature, a user-customizable instruction set.
Using the supplied customization tools, customers can extend the Xtensa base instruction set by adding new user-defined instructions. Extensions can include SIMD instructions, new register files, and additional data transfer interfaces for multiprocessor communication. After the final processor configuration is made and submitted, Cadence's processor generator service builds the configured Xtensa IP core, processor design kit, and software development kit. This process is highly automated so designers can quickly experiment with different instruction additions, testing the performance improvements and power trade-offs of the various alternatives.
The processor kit contains items necessary to integrate the configured IP into the customer's chip design environment: the core's hardware description (in synthesizeable RTL or physical post-layout form), timing & I/O constraints, requirements for technology-specific RAMs/caches/FIFOs. The software kit is built on the Eclipse-based integrated development environment, and uses a GNU Compiler Collection-derived tool-chain: C/C++ compiler, assembler, linker, debugger. An instruction set simulator enables customers to begin application development before actual hardware is available.
Xtensa instruction set
The Xtensa instruction set is designed to meet the diverse requirements of dataplane processing. This 32-bit architecture features a compact 16- and 24-bit instruction set with modeless switching for maximum power efficiency and performance. The base instruction set has 80 RISC instructions and includes a 32-bit ALU, up to 64 general-purpose 32-bit registers, and six special-purpose registers.
Adoption
AMD's TrueAudio and Unified Video Decoder are ASICs based on Xtensa.
HiFi Audio and Voice DSP IPSimplified block diagrams of HiFi Audio Engine and Xtensa LX.


  • HiFi Mini Audio DSP — The smallest, lowest power DSP core for always-listening voice trigger and voice recognition
  • HiFi 2 Audio DSP — This highly efficient DSP core provides the lowest power MP3 audio processing
  • HiFi EP Audio DSP — A superset of HiFi 2 with advanced optimizations for DTS Master Audio, improved voice pre- and post-processing, and improved cache memory subsystem
  • HiFi 3 Audio DSP — Full 32-bit processing makes this DSP super efficient for many of the audio enhancement algorithms, wideband voice codecs, and multi-channel audio
  • New - The HiFi 4 DSP - 2X HiFi 3 performance for DSP intensive applications including emerging multi-channel object-based audio standards.
Adoption
[color=rgba(0, 0, 0, 0.7019607843137254)]AMD TrueAudio, found e.g. in the PlayStation 4, in "Kaveri" desktop APUs and in a very few of AMD's graphics cards, is based on the Cadence Tensilica HiFi EP Audio DSP.
The ESP8266 and ESP32 embedded Wi-Fi chip utilises the Xtensa as its main CPU core.
[color=rgba(0, 0, 0, 0.7019607843137254)]Microsoft HoloLens uses special custom-designed TSMC-fabricated 28nm coprocessor that has 24 Tensilica DSP cores. It has around 65 million logic gates, 8MB of SRAM, and an additional layer of 1GB of low-power DDR3 RAM.[4]


History
  • In 1997 Tensilica was founded by Chris Rowen.
  • In 2002 Tensilica released support for flexible length instruction encodings, known as FLIX.
  • In 2013 Cadence Design Systems acquired Tensilica.


Company name
The brand name Tensilica is a combination of the word tensile, meaning capable of being extended, and the word silicon, the element of which integrated circuits are primarily made.










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发表于 2016-12-21 17:34 | 显示全部楼层
感谢介绍!
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发表于 2016-12-26 21:18 | 显示全部楼层
了解了解
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